1. Field of the Invention
The present invention pertains to the polishing of wafers, especially wafers of semiconductor material bearing electronic circuit elements.
2. Description of the Related Art
The production of semiconductor devices, such as integrated circuits, begins with the preparation of high quality raw semiconductor wafers. Because of the relative purity of the semiconductor material, even the raw, unprocessed semiconductor wafers have a substantial cost. Thin layers of expensive materials are then stacked on top of a raw silicon wafer and then on top of one another in succession. A variety of carefully controlled operations such as metalization, sputtering, and ion implantation are used to form the respective layers. The thickness of the layers is relatively small, typically on the on the order of several molecular dimensions.
During integrated circuit production, as circuit layers are successively stacked one on top of the other, an extremely flat working surface is required at each stage in the wafer production. Flatness is attained by polishing on a platen, typically in the presence of a chemical medium, and thus the polishing processes are typically referred to as chemical/mechanical polishing (CMP). The semiconductor wafers, because of their material composition and relatively thin dimensions, are fragile, susceptible to damage by over-bending and chipping caused by inadvertent contact with the wafer edge. As mentioned, at each stage in the wafer production process, the wafers must be transferred to polishing equipment, to be polished to a flatness defined by ever increasingly demanding tolerances. For example, wafer flatness has, in the past, been typically held to 120 micro inches or less over the entire surface of a wafer of 8-inch diameter. Recently, the same numerical flatness requirements have been applied to a new generation of wafers of approximately 12 inches or 300 millimeters in diameter. Thus, for this reason alone, the polishing tolerances are becoming increasingly stringent. Further, it is expected that the industry will require more complete utilization of the wafer surface, even to the extreme edge regions of the wafer.
After polishing to achieve a desired flat working surface, a new layer of circuit structures is formed on the wafer so as to become mechanically and eventually electronically linked to underlying layers, now incorporated in the growing wafer body. Layer formation techniques typically involve depositing films on the wafer surface, in order to selectively confine the next layer addition to carefully defined portions of the wafer surface. When no longer needed, such films are routinely removed using a variety of chemically active solutions.
A need has arisen, from time to time, to provide isolation of wafers during their preparation. One concern is the possibility of introducing particles or droplets of unwanted material from one wafer to another. For example, wafers, and particularly wafer surfaces, have chemical reactivities which vary widely from the conditions at one stage of preparation to another. Such problems may arise when different types of chemistries are employed to remove a film from a previous operation, or to prepare a wafer surface for a subsequent operation, for example. The different chemistries themselves may be incompatible with one another, and accordingly, a chemical isolation is required throughout the various steps of wafer handling and processing. Particles generated in a cleaning, buffing or scrubbing of one wafer must not be allowed to transfer to other wafers, particularly those which are regarded as "clean" and not requiring further preparations before carrying out the next production step. Thus, the need arises to provide polishing systems of greater flexibility and adaptability for different materials and processes.